As the physical limitation of scaling NAND flash memory is being reached in the near future, several classes of materials which demonstrate bi-stable resistances have been studied for high density non-volatile memory (NVM) applications for the next generation. Among them, transition-metal-oxide (TMO) based resistive random access memory (RRAM) cells attract lots of attention owing to their fast switching, excellent reliability (retention & endurance), good scalability and CMOS (complementary metal-oxide-semiconductor) compatibility. Therefore, RRAM is a promising candidate for high density NVM.
FIG. 1A shows a schematic perspective view of a generalized 2×2 array cross-bar memory structure 100, wherein one bit cell arrangement (e.g. as represented by the dotted rectangle 101) of the array 100 consists of a RRAM cell (1R) only, sandwiched between the conductive word lines (WL) and bit lines (BL). For example, the array 100 includes a RRAM 102a, of the bit cell 101, sandwiched between the bit line, BLn, 104a and the word line, WLm, 106a, and a RRAM 102b sandwiched between the bit line, BLn+1, 104b and the word line, WLm+1, 106b. 
In order to eliminate the cross-talk interference from neighbouring RRAM cells in an array structure and to avoid the read error effect, a selector (or rectifying element), implemented either by 1D (diode) or by 1T (transistor), is required in each cell.
FIG. 1B shows a schematic of a generalized 3×3 array 1T-1R (a transistor and a RRAM cell) memory structure 110. For a 1T-1R memory configuration, each cell arrangement 111 includes a RRAM 112 electrically coupled with a transistor 113. The transistor 113 includes a first source/drain terminal 114, which may be electrically coupled to a terminal of the RRAM 112, a second source/drain terminal 115 and a gate terminal 116. As shown in FIG. 1B for the memory structure 110, as a non-limiting example, the one bit cell arrangement (e.g. as represented by the dotted circle 111a) includes the RRAM 112a electrically coupled to the transistor 113a, where the cell arrangement 111a is electrically coupled between the bit line, BL2, 117 and the source line, SL2, 118. The gate terminal of the transistor 113a is electrically coupled to the word line, WL2, 119.
FIG. 1C shows a schematic of a generalized 2×2 array 1D-1R memory structure 130 having a cross-bar architecture. For a 1D-1R memory configuration, each cell arrangement 131 includes a RRAM 132 electrically coupled with a diode selector 133. As shown in FIG. 1C, the 2×2 array memory structure 130 includes a first one bit cell arrangement 131a sandwiched between the bit line, BLn, 136a and the word line, WLm, 138a, a second one bit cell arrangement 131b sandwiched between the bit line, BLn+1, 136b and the word line, WLm, 138a, a third one bit cell arrangement 131c sandwiched between the bit line, BLn, 136a and the word line, WLm+1, 138b, and a fourth one bit cell arrangement 131d sandwiched between the bit line, BLn+1, 136b and the word line, WLm+1, 138b. As a non-limiting example, the third bit cell arrangement 131c includes the RRAM 132c electrically coupled to the diode 133c, where the diode 133c is arranged or formed over or on top of the RRAM 132c, vertically, between BLn, 136a and WLm+1 138b. FIG. 1D shows a schematic top view of the 1D-1R memory structure 130 of FIG. 1C, illustrating a period or pitch of 2 F (F refers to the minimum feature size) between adjacent one bit cell arrangements (e.g. between the first one bit cell arrangement 131a and the third one bit cell arrangement 131c), thereby realizing a cell arrangement size of 4 F2 footprint.
FIG. 1E shows a schematic cross sectional view of a 1D-1R memory cell arrangement 150. The memory cell arrangement 150 includes a stack arrangement of a p-doped layer (P-type) 151 and an n-doped layer (N-type) 152, which collectively form a diode 153, which may be equivalent to the diode 133 of FIG. 1C. The memory cell arrangement 150 further includes a top electrode (TE) 154, a resistive layer 155 and a bottom electrode (BE) 156, which collectively form a RRAM cell 157, which may be equivalent to the RRAM 132 of FIG. 1C.
Considering the fabrication technology for the traditional transistor, stacked 1T-1R (RRAM) structures for high density applications are not very suitable due to their high temperature processes, which make it difficult to form three-dimensional (3-D) multi-stacks, and large unit cell sizes, which is determined by the transistor.
Therefore, the vertical cross-bar architecture has attracted a lot of interest for high density 3-dimensional (3D) integration, with RRAM cells (and diodes) sandwiched between the word and bit lines, realizing a cell arrangement size of 4 F2 (F refers to the minimum feature size) footprint, as illustrated in FIGS. 1C and 1D. Furthermore, the vertical 1D-1R cross-bar architecture may have a 4 F2/n footprint, where n is the number of stacked layers. Nevertheless, the requirements for the diode selector, including high forward current density, high on/off current ratio, low processing temperature and high CMOS compatibility, have been found to be very difficult to be met simultaneously in the vertical 1D-1R architecture. For example, the diode stack (material) is not CMOS friendly. Furthermore, the current (density or area) needs to be increased for the diode to meet the RRAM switching requirements. In addition, the current through the diode may not be big enough to trigger the RRAM switching with size scaling.
In addition, as illustrated in FIG. 1C, the RRAM (1R) (e.g. 132c) and the diode (1D) (e.g. 133c) are stacked vertically in between WL (e.g. 138b) and BL (e.g. 136a) in the conventional 1D-1R cross-bar architecture. Moreover, the critical dimensions for both the RRAM and the diode are exactly the same, which means that the size of the diode has to scale together with that of the RRAM cell. This means that as the size of the RRAM cell is increased or decreased, the size of the diode needs to correspondingly increase or decrease by the same amount.